1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM) device having a burn-in test function.
2. Description of the Related Art
In a semiconductor memory device, before its shipment, a burn-in test is carried out to stabilize the characteristics and reveal defects.
In such a burn-in test, a power supply voltage such as 7V which is higher than a usual power supply voltage such as 5V is applied to a semiconductor memory device for a long time such as about 8 to 10 hours. The higher the power supply voltage, the larger the screening effect. Also, the longer the burn-in test time, the larger the screening effect.
In a burn-in test, since peripheral circuits entirely operate at each cycle, sufficient stress is applied thereto. On the other hand, since only selected memory cells operate at each cycle, stress applied thereto is not sufficient. For example, in a 16 Mbit-DRAM device, stress is applied to only 1/2000 of memory cells.
Therefore, to order to enhance the screening effect of the burn-in test, a larger number of memory cells are simultaneously selected using a voltage higher than a power supply voltage, which also reduces the burn-in test time (see: JP-A-6-76599). This will be explained later in detail.
In the above-mentioned prior art semiconductor memory device, however, since there is no means for detecting such a high voltage, if the voltage at the word lines is so high that too large a stress is applied to the memory cells. In this case, larger stress is applied to the peripheral circuit of the device. On the contrary, if the voltage at the word lines is too low due to the large number of the simultaneously driven word lines, the capacity of a word line level generating circuit needs to be larger, which decreases the integration.